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DATA SHEET
MOS INTEGRATED CIRCUIT
PD784031Y
16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
The PD784031Y is based on the PD784031 with an I2C bus control function appended, and is ideal for applications in audio-visual systems. The PD784031Y is a ROM-less version of PD784035Y and 784036Y. The functions are explained in detail in the following User's Manual. Be sure to read this manual when designing your system.
PD784038, 784038Y Subseries User's Manual - Hardware : U11316E
78K/IV Series User's Manual - Instruction : U10905E
FEATURES
78K/IV Series Pin-compatible with PD78234 Subseries, Timer/counter 16-bit Timer/counter x 3 units 16-bit Timer x 1 unit Standby function HALT/STOP/IDLE mode Clock division function Watchdog timer: 1 channel A/D converter: 8-bit resolution x 8 channels D/A converter: 8-bit resolution x 2 channels bus): Supply voltage: VDD = 2.7 to 5.5 V I 2C
PD784026 Subseries, and PD784038
Subseries Minimum instruction execution time: 125 ns (@ 32-MHz operation) I/O ports: 46 Serial interface: 3 channels UART/IOE (3-wire serial I/O): 2 channels CSI (3-wire serial I/O, 2-wire serial I/O, 1 channel PWM output: 2 outputs
APPLICATION FIELDS
Cellular phones, cordless phones, audio-visual systems, etc.
ORDERING INFORMATION
Part Number Package Internal ROM (Bytes) Internal RAM (Bytes)
PD784031YGC-3B9 PD784031YGC-8BT PD784031YGK-BE9
80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm) 80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
None None None
2048 2048 2048
The information in this document is subject to change without notice. Document No. U11504EJ1V0DS00 (1st edition) Date Published July 1997 N Printed in Japan The mark shows major revised points.
(c)
1996
PD784031Y
78K/IV SERIES PRODUCT DEVELOPMENT
: Under mass production : Under development
I2C bus supported PD784038Y Standard models PD784026 Enhanced A/D, 16-bit timer, and power management PD784038 Enhanced internal memory capacity, pin compatible with the PD784026 Multimaster I2C bus supported PD784216Y PD784216 100 pins, enhanced I/O and internal memory capacity PD784054
Multimaster I2C bus supported PD784225Y PD784225 80 pins, added ROM correction Multimaster I2C bus supported PD784218Y PD784218 Enhanced internal memory capacity, added ROM correction
PD784046 ASSP models PD784908 Equipped with IEBusTM controller PD78F4943 For CD-ROM, 56-Kbyte flash memory PD784915 Equipped with analog circuit for software servo control VCR, enhanced timer Multimaster I2C bus supported PD784928Y PD784928 Enhanced function of the PD784915 Equipped with 10-bit A/D
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PD784031Y
FUNCTIONS
Item Number of basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space I/O port Total Input I/O Output Pins with ancillary functionNote Pins with pullup resistor LEDs direct drive output Transistor direct drive Real-time output port Timer/counter ROM RAM 113 8 bits x 16 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping) 125 ns/250 ns/500 ns/1000 ns (at 32 MHz) None 2048 bytes 1 Mbytes with program and data spaces combined 46 8 34 4 32 8 8 4 bits x 2, or 8 bits x 1 Timer/counter 0: Timer register x 1 Capture register x 1 Compare register x 2 (16 bits) Timer/counter 1: Timer register x 1 Capture register x 1 (8/16 bits) Capture/compare register x 1 Compare register x 1 Timer/counter 2: Timer register x 1 Capture register x 1 (8/16 bits) Capture/compare register x 1 Compare register x 1 Timer 3: (8/16 bits) PWM output Serial interface A/D converter D/A converter Watchdog timer Standby Interrupt Hardware source Software source Non-maskable Maskable Timer register x 1 Compare register x 1 Pulse output * Toggle output * PWM/PPG output * One-shot pulse output Pulse output * Real-time output (4 bits x 2) Function
Pulse output * Toggle output * PWM/PPG output
12-bit resolution x 2 channels UART/IOE (3-wire serial I/O) : 2 channels (on-chip baud rate generator) CSI (3-wire serial I/O, 2-wire serial I/O, I2C bus) : 1 channel 8-bit resolution x 8 channels 8-bit resolution x 2 channels 1 channel HALT/STOP/IDLE mode 24 (internal: 17, external: 7 (variable sampling clock input: 1)) BRK instruction, BRKCS instruction, operand error Internal: 1, external: 1 Internal: 16, external: 6 * 4 programmable priority levels * 3 processing styles: vectored interrupt/macro service/context switching
Supply voltage Package
VDD = 2.7 to 5.5 V 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm) 80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
Note The pins with ancillary function are included in the I/O pins.
3
PD784031Y
CONTENTS
1. DIFFERENCES AMONG MODELS IN PD784038Y SUBSERIES .................................................. 6 2. MAJOR DIFFERENCES FROM PD784026 SUBSERIES AND PD78234 SUBSERIES .............. 7 3. PIN CONFIGURATION (Top View) ................................................................................................... 8 4. BLOCK DIAGRAM ............................................................................................................................ 10 5. PIN FUNCTION ............................................................................................................................... 11
5.1 5.2 5.3 Port Pins ................................................................................................................................................ 11 Non-port Pins ........................................................................................................................................ 12 Types of Pin I/O Circuits and Connections for Unused Pins ............................................................ 14
6.
CPU ARCHITECTURE .................................................................................................................... 17
6.1 6.2 Memory Space ....................................................................................................................................... 17 CPU Registers ....................................................................................................................................... 19 6.2.1 6.2.2 6.2.3 General-purpose registers .......................................................................................................... 19 Control registers .......................................................................................................................... 20 Special function registers (SFRs) ............................................................................................... 21
7.
PERIPHERAL HARDWARE FUNCTIONS ..................................................................................... 26
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 Ports ....................................................................................................................................................... 26 Clock Generation Circuit ...................................................................................................................... 27 Real-time Output Port ........................................................................................................................... 29 Timer/Counter ........................................................................................................................................ 30 PWM Output (PWM0, PWM1) ................................................................................................................ 32 A/D Converter ........................................................................................................................................ 33 D/A Converter ........................................................................................................................................ 34 Serial Interface ...................................................................................................................................... 35 7.8.1 7.8.2 7.9 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ...................................................... 36 Clocked serial interface (CSI) ..................................................................................................... 38
Edge Detection Function ...................................................................................................................... 39
7.10 Watchdog Timer .................................................................................................................................... 40
8.
INTERRUPT FUNCTION ................................................................................................................. 41
8.1 8.2 8.3 8.4 8.5 Interrupt Sources .................................................................................................................................. 41 Vectored Interrupt ................................................................................................................................. 43 Context Switching ................................................................................................................................. 44 Macro Service ........................................................................................................................................ 44 Application Example of Macro Service ............................................................................................... 45
4
PD784031Y
9.
LOCAL BUS INTERFACE .............................................................................................................. 47
9.1 9.2 9.3 9.4 9.5 Memory Expansion ............................................................................................................................... 47 Memory Space ....................................................................................................................................... 48 Programmable Wait .............................................................................................................................. 49 Pseudo Static RAM Refresh Function ................................................................................................. 49 Bus Hold Function ................................................................................................................................ 49
10. STANDBY FUNCTION .................................................................................................................... 50 11. RESET FUNCTION ......................................................................................................................... 51 12. INSTRUCTION SET ........................................................................................................................ 52 13. ELECTRICAL SPECIFICATIONS ................................................................................................... 57 14. PACKAGE DRAWINGS .................................................................................................................. 77 15. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 80 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 82 APPENDIX B. RELATED DOCUMENTS ............................................................................................... 84
5
PD784031Y
1. DIFFERENCES AMONG MODELS IN PD784038Y SUBSERIES
The only difference among the PD784031Y, 784035Y, 784036Y, 784037Y, and 784038Y lies in the internal memory capacity. The PD78P4038Y is provided with a 128-Kbyte one-time PROM or EPROM instead of the mask ROM of the
PD784035Y, 784036Y, 784037Y, and 784038Y. These differences are summarized in Table 1-1.
Table 1-1. Differences among Models in PD784038Y Subseries
Part Number Item Internal ROM None 48 Kbytes (mask ROM) 64 Kbytes (mask ROM) 96 Kbytes (mask ROM) 128 Kbytes (mask ROM) 128 Kbytes (one-time PROM or EPROM) Internal RAM Package 2048 bytes 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm) 80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin ceramic WQFN (14 x 14 mm) 3584 bytes 4352 bytes
PD784031Y
PD784035Y
PD784036Y
PD784037Y
PD784038Y
PD78P4038Y
6
PD784031Y
2. MAJOR DIFFERENCES FROM PD784026 SUBSERIES AND PD78234 SUBSERIES
Series Name Item Number of basic instructions (mnemonics) Minimum instruction execution time 125 ns (@ 32-MHz operation) Memory space (program/data) Timer/counter 1 Mbytes combined 16-bit timer/counter x 1 8-/16-bit timer/counter x 2 8-/16-bit timer x 1 Clock output function Watchdog timer Serial interface Provided Provided UART/IOE (3-wire serial I/O) x 2 channels CSI (3-wire serial I/O, 2-wire serial I/O, I2C busNote) x 1 channel Interrupt Context switching Priority Standby function Operating clock Pin function MODE pin 4 levels HALT/STOP/IDLE mode Selectable from fXX/2, fXX/4, fXX/8, and fXX/16 None 2 levels HALT/STOP mode Fixed to fXX/2 Specifies ROM-less mode (always high level with Provided None UART/IOE (3-wire serial I/O) x 2 channels CSI (3-wire serial I/O, SBI) x 1 channel 160 ns (@ 25-MHz operation) 333 ns (@ 12-MHz operation) 64 Kbytes/1 Mbytes 16-bit timer/counter x 1 8-bit timer/counter x 2 8-bit timer x 1 None None UART x 1 channel CSI (3-wire serial I/O, SBI) x 1 channel
PD784038Y Subseries PD784038 Subseries
113
PD784026 Subseries
PD78234 Subseries
65
PD78233 and 78237)
TEST pin Device test pin Usually, low level Package 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm) 80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin ceramic WQFN (14 x 14 mm): 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm): 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm) 94-pin plastic QFP (20 x 20 mm) 84-pin plastic QFJ (1150 x 1150 mil) 94-pin ceramic WQFN (20 x 20 mm): None
PD784021 only
80-pin ceramic WQFN (14 x 14 mm):
PD78P4026 only
PD78P4038Y and
78P4038 only
PD78P238 only
Note
PD784038Y Subseries only
7
PD784031Y
3. PIN CONFIGURATION (Top View)
* 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm)
PD784031YGC-3B9
* 80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm)
PD784031YGC-8BT
* 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
PD784031YGK-BE9
P31/TxD/SO1 P30/RxD/SI1 P27/SI0 P26/INTP5 P25/INTP4/ASCK/SCK1 P24/INTP3 P23/INTP2/CI P22/INTP1 P21/INTP0 P20/NMI AVREF3 AVREF2 ANO1 ANO0 AVSS AVREF1 AVDD P77/ANI7 P76/ANI6 P75/ANI5
P32/SCK0/SCL P33/SO0/SDA P34/TO0 P35/TO1 P36/TO2 P37/TO3 RESET VDD1 X2 X1 VSS1 P00 P01 P02 P03 P04 P05 P06 P07 P67/REFRQ/HLDAK
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 2021 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 4041
P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 VDD0 P17 P16 P15 P14/TxD2/SO2 P13/TxD2/SI2 P12/ASCK2/SCK2 P11/PWM1 P10/PWM0 TESTNote VSS0 ASTB AD0 AD1 AD2
Note Directly connect the TEST pin to VSS0.
8
P66/WAIT/HLDRQ WR RD P63/A19 P62/A18 P61/A17 P60/A16 A15 A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3
PD784031Y
A8 to A19 AD0 to AD7 ANI0 to ANI7 ANO0, ANO1 ASCK, ASCK2 ASTB AVDD AVSS CI HLDAK HLDRQ INTP0 to INTP5 NMI P00 to P07 P10 to P17 P20 to P27 P30 to P37
: Address Bus : Address/Data Bus : Analog Input : Analog Output : Asynchronous Serial Clock : Address Strobe : Analog Power Supply : Analog Ground : Clock Input : Hold Acknowledge : Hold Request : Interrupt from Peripherals : Non-maskable Interrupt : Port0 : Port1 : Port2 : Port3
P70 to P77 PWM0, PWM1 RD REFRQ RESET RxD, RxD2 SCK0 to SCK2 SCL SDA SI0 to SI2 SO0 to SO2 TEST TO0 to TO3 TxD, TxD2 VDD0, VDD1 VSS0, VSS1 WAIT WR X1, X2
: Port7 : Pulse Width Modulation Output : Read Strobe : Refresh Request : Reset : Receive Data : Serial Clock : Serial Clock : Serial Data : Serial Input : Serial Output : Test : Timer Output : Transmit Data : Power Supply : Ground : Wait : Write Strobe : Crystal
AVREF1 to AVREF3 : Reference Voltage
P60 to P63, P66, P67 : Port6
9
PD784031Y
4. BLOCK DIAGRAM
UART/IOE2 BAUD-RATE GENERATOR UART/IOE1 BAUD-RATE GENERATOR RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2
NMI INTP0 to INTP5
PROGRAMMABLE INTERRUPT CONTROLLER
INTP3 TO0 TO1
TIMER/COUNTER0 (16 BITS)
INTP0
TIMER/COUNTER1 (16 BITS)
CLOCKED SERIAL INTERFACE
SCK0/SCL SO0/SDA SI0 ASTB AD0 to AD7 A8 to A15 A16 to A19 RD WR WAIT/HLDRQ REFRQ/HLDAK P00 to P07 P10 to P17 P20 to P27 P30 to P37 P60 to P63
INTP1 INTP2/CI TO2 TO3
TIMER/COUNTER2 (16 BITS)
78K/IV CPU CORE BUS I/F
TIMER3 (16 BITS)
P00 to P03 P04 to P07
REAL-TIME OUTPUT PORT
PORT0 PORT1
PWM0 PWM1 ANO0 ANO1 AVREF2 AVREF3 ANI0 to ANI7 AVDD AVREF1 AVSS INTP5
PWM
RAM
PORT2 PORT3
D/A CONVERTER PORT6
P66 to P67 A/D CONVERTER WATCHDOG TIMER PORT7 SYSTEM CONTROL P70 to P77 RESET TEST X1 X2 VDD0, VDD1 VSS0, VSS1
10
PD784031Y
5. PIN FUNCTION 5.1 Port Pins
Pin Name P00 to P07 I/O I/O Alternate Function - Port 0 (P0): * 8-bit I/O port * Can be used as real-time output port (4 bits x 2). * Can be set in input or output mode bitwise. * Pins set in input mode can be connected to internal pull-up resistors by software. * Can drive transistor. P10 P11 P12 P13 P14 P15 to P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 to P37 P60 to P63 P66 P67 I/O I/O Input NMI INTP0 INTP1 INTP2/CI INTP3 INTP4/ASCK/SCK1 INTP5 SI0 RxD/S1 TxD/SO1 SCK0/SCL SO0/SDA TO0 to TO3 A16 to A19 WAIT/HLDRQ REFRQ/HLDAK Port 6 (P6): * P60 through P63 is dedicated ports for output. * P66 and P67 can be set in input or output mode bitwise. * Pins set in input mode can be connected to internal pull-up resistors by software. P70 to P77 I/O AN10 to AN17 Port 7 (P7): * 8-bit I/O port * Can be set in input or output mode bitwise. Port 3 (P3): * 8-bit I/O port * Can be set in input or output mode bitwise. * Pins set in input mode can be connected to internal pull-up resistors by software. I/O PWM0 PWM1 ASCK2/SCK2 RxD2/SI2 TxD2/SO2 - Port 2 (P2): * 8-bit input port * P20 cannot be used as general-purpose port pin (non-maskable interrupt). However, its input level can be checked by interrupt routine. * P22 through P27 can be connected to internal pull-up resistors by software in 6-bit units. * P25/INTP4/ASCK/SCK1 pin can operate as SCK1 output pin if so specified by CSIM1. Port 1 (P1): * 8-bit I/O port * Can be set in input or output mode bitwise. * Pins set in input mode can be connected to internal pull-up resistors by software. * Can drive LEDs. Function
11
PD784031Y
5.2 Non-port Pins
Pin Name TO0 to TO3 CI RxD RxD2 TxD TxD2 ASCK ASCK2 SDA SI0 SI1 SI2 SO0 SO1 SO2 SCK0 SCK1 SCK2 SCL NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 AD0 to AD7 A8 to A15 A16 to A19 RD WR WAIT REFRQ HLDRQ HLDAK ASTB I/O Output Output Output Output Input Output Input Output Output Input I/O Output I/O Input Input Output I/O Output Input Input Alternate Function P34 to P37 P23/INTP2 P30/SI1 P13/SI2 P31/SO1 P14/SO2 P25/INTP4/SCK1 P12/SCK2 P33/SO0 P27 P30/RxD P13/RxD2 P33/SDA P31/TxD P14/TxD2 P32/SCL P25/INTP4/ASCK P12/ASCK2 P32/SCK0 P20 P21 P22 P23/CI P24 P25/ASCK/SCK1 P26 - - P60 to P63 - - P66/HLDRQ P67/HLDAK P66/WAIT P67/REFRQ - Timer output Count clock input to timer/counter 2 Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data input/output (2-wire serial I/O, I2C bus) Serial data input (3-wire serial I/O0) Serial data input (3-wire serial I/O1) Serial data input (3-wire serial I/O2) Serial data output (3-wire serial I/O0) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial clock input/output (3-wire serial I/O0) Serial clock input/output (3-wire serial I/O1) Serial clock input/output (3-wire serial I/O2) Serial clock input/output (2-wire serial I/O, I2C bus) External interrupt requests - * Count clock input to timer/counter 1 * Capture trigger signal of CR11 or CR12 * Count clock input to timer/counter 2 * Capture trigger signal of CR22 * Count clock input to timer/counter 2 * Capture trigger signal of CR21 * Count clock input to timer/counter 0 * Capture trigger signal of CR02 - Conversion start trigger input to A/D converter Time-division address/data bus (for external memory connection) Higher address bus (for external memory connection) Higher address when address is extended (for external memory connection) Read strobe to external memory Write strobe to external memory Wait insertion Refresh pulse output to external pseudo static memory Bus hold request input Bus hold acknowledge output Latch timing output of time-division address (A0 through A7) (when accessing external memory) Function
12
PD784031Y
Pin Name RESET X1 X2 ANI0 to ANI7 ANO0, ANO1 AVREF1 AVREF2, AVREF3 AVDD AVSS VDD0Note 1 VDD1Note 1 VSS0Note 2 VSS1Note 2 TEST
I/O Input Input - Input Output -
Alternate Function - - Chip reset
Function
Crystal connection for system clock oscillation (Clock can also be input to X1.)
P70 to P77 - -
Analog voltage input to A/D converter Analog voltage output from D/A converter Reference voltage to A/D converter Reference voltage to D/A converter A/D converter power supply A/D converter GND Power supply of port Power supply except for port GND of port GND except for port Directly connect to VSS0 (IC test pin).
Notes 1. Provide the same potential to VDD0 and VDD1. 2. Provide the same potential to VSS0 and VSS1.
13
PD784031Y
5.3 Types of Pin I/O Circuits and Connections for Unused Pins
Table 5-1 shows types of pin I/O circuits and the connections for unused pins. For the input/output circuit of each type, refer to Figure 5-1. Table 5-1. Types of Pin I/O Circuits and Connections for Unused Pins (1/2)
Pin Name P00 to P07 P10/PWM0 P11/PWM1 P12/ASCK2/SCK2 P13/RxD2/SI2 P14/TxD2/SO2 P15 to P17 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 8-C I/O Input: Connect to VDD0. Output: Open P26/INTP5 P27/SI0 P30/RxD/SI1 P31/TxD/SO1 P32/SCK0/SCL P33/SO0/SDA P34/TO0 to P37/TO3 AD0 to AD7 A8 to A15 P60/A16 to P63/A19 RD WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0 to P77/ANI7 20-A I/O Input: Connect to VDD0. Output: Open Input: Connect to VDD0 or VSS0. Output: Open ANO0, ANO1 ASTB 12 4-B Output Open OutputNote Open 5-H 10-B 5-H I/O Input: Connect to VDD0. Output: Open 2-C Input Connect to VDD0. 2-C Connect to VDD0. 2 Input Connect to VDD0 or VSS0. 8-C 5-H I/O Circuit Type 5-H I/O I/O Recommended Connection for Unused Pins Input: Connect to VDD0. Output: Open
Note I/O circuit type of these pins is 5-H. However these pins perform only as output by an internal circuit.
14
PD784031Y
Table 5-1. Types of Pin I/O Circuits and Connections for Unused Pins (2/2)
Pin Name RESET TEST AVREF1 to AVREF3 AVSS AVDD Connect to VDD0. I/O Circuit Type 2 1-A - I/O Input Directly connect to VSS0. Connect to VSS0. Recommended Connection for Unused Pins -
Caution
Connect an I/O pin whose input/output mode is unstable to VDD0 via a resistor of several 10 k (especially if the voltage on the reset input pin rises higher than the low-level input level on power application or when the mode is switched between input and output by software).
Remark Because the circuit type numbers shown in the above table are commonly used with all the models in the 78K Series, these numbers of some models are not serial (because some circuits are not provided to some models).
15
PD784031Y
Figure 5-1. Types of Pin I/O Circuits
Type 1-A VDD0 P IN N VSS0 Type 2 IN P pullup enable Type 2-C VDD0
IN
Schmitt trigger input with hysteresis characteristics
Schmitt trigger input with hysteresis characteristics
Type 5-H
VDD0
Type 4-B VDD0 data P OUT
pullup enable data
P VDD0 P IN/OUT
output disable
N VSS0
output disable input enable Type 12
N VSS0
Push-pull output that can go into a high-impedance state (with both P-ch and N-ch off) Type 8-C VDD0
pullup enable data
P VDD0 P IN/OUT Analog output voltage N P OUT
output disable
N VSS0
Type 10-B
VDD0
Type 20-A data
VDD0 P IN/OUT
pullup enable VDD0 data P
P output disable IN/OUT Comparator N VSS0 input enable P N N VSS0
+ -
open drain output disable
AVSS AVREF (threshold voltage)
16
PD784031Y
6. CPU ARCHITECTURE 6.1 Memory Space
A memory space of 1 Mbytes can be accessed. Mapping of the internal data area (special function registers and internal RAM) can be specified the LOCATION instruction. The LOCATION instruction must be always executed after reset cancellation, and must not be used more than once. (1) When LOCATION 0 instruction is executed The internal data area is mapped in 0F700H to 0FFFFH.
(2) When LOCATION 0FH instruction is executed The internal data area is mapped in FF700H to FFFFFH.
17
18
On execution of LOCATION 0 instruction
F F F F FH
Figure 6-1. Memory Map of PD784031Y
On execution of LOCATION 0FH instruction
F F F F FH F F FDFH F F FD0H FFF 0 0H F FEF FH
Special function registers (SFR) (256 bytes)
0 FEF FH
F FEF FH
External memory (960 Kbytes)
0 FE8 0H 0 FE 7 FH
General-purpose registers (128 bytes)
FFE8 0H F FE 7 FH FF 7 0 0H F F 6 F FH
Internal RAM (2 Kbytes)
1 0 0 0 0H 0 F F F FH 0 F FDFH 0 F FD0H 0 FF 0 0H 0 FEF FH 0 FD0 0H 0 FCF FH
0 FE3 1H
Special function registers (SFR) (256 bytes)
0 FE0 6H
Macro service control word area (44 bytes) Data area (512 bytes)
F F E 31 H FFE0 6H
Internal RAM (2 Kbytes)
0 FD0 0H 0 FCF FH
F FD0 0H F FCF FH
Program/data area (1536 bytes)
0 F 7 0 0H FF 7 0 0H
External memory (1046272 bytes)
0 F 7 0 0H 0 F 6 F FH
Note
External memory (63232 bytes)
0 1 0 0 0H 0 0 F F FH
0 0 F F FH
CALLF entry area (2 Kbytes)
0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H 0 0 0 0 0H 0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 1 0 0 0 0H 0 F F F FH
Note
CALLT table area (64 bytes) Vector table area (64 bytes)
0 0 0 0 0H
PD784031Y
Note Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.
PD784031Y
6.2 CPU Registers
6.2.1 General-purpose registers Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit register. Of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24-bit address specification registers. Eight banks of these registers are available which can be selected by using software or the context switching function. The general-purpose registers except V, U, T, and W registers for address expansion are mapped to the internal RAM. Figure 6-2. General-purpose Register Format
A (R1) AX (RP0) B (R3) BC (RP1) R5 RP2 R7 RP3 V VVP (RG4) U R11 R9 VP (RP4)
X (R0) C (R2) R4 R6 R8
R10
T
UP (RP5) UUP (RG5) D (R13) E (R12) DE (RP6) TDE (RG6) H (R15) L (R14) 8 banks WHL (RG7) HL (RP7) ) indicate an absolute name.
W
Parentheses (
Caution
Registers R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of the PSW to 1. However, use this function only for recycling the program of the 78K/III Series.
19
PD784031Y
6.2.2 Control registers (1) Program counter (PC) The program counter is a 20-bit register whose contents are automatically updated when the program is executed. Figure 6-3. Program Counter (PC) Format
19 PC 0
(2) Program status word (PSW) This register holds the statuses of the CPU. Its contents are automatically updated when the program is executed. Figure 6-4. Program Status Word (PSW) Format
15 PSWH PSW 7 PSWL S 6 Z 5 RSS
Note
14 RBS2
13 RBS1
12 RBS0
11 -
10 -
9 -
8 -
UF
4 AC
3 IE
2 P/V
1 0
0 CY
Note This flag is provided to maintain compatibility with the 78K/III Series. Be sure to clear this flag to 0, except when the software for the 78K/III Series is used. (3) Stack pointer (SP) This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the higher 4 bits of this pointer. Figure 6-5. Stack Pointer (SP) Format
23 SP 0 0 0 0 20 0
20
PD784031Y
6.2.3 Special function registers (SFRs) The special function registers, such as the mode registers and control registers of the internal peripheral hardware, are registers to which special functions are allocated. These registers are mapped to a 256-byte space of addresses 0FF00H through 0FFFFHNote. Note On execution of the LOCATION 0 instruction. FFF00H through FFFFFH on execution of the LOCATION 0FH instruction. Caution Do not access an address in this area to which no SFR is allocated. If such an address is accessed by mistake, the PD784031Y may be in the deadlock status. This deadlock status can be cleared only by inputting the reset signal. Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows: * Symbol ................................ Symbol indicating an SFR. This symbol is reserved for NEC's assembler (RA78K4). It can be used as an sfr variable by the #pragma sfr command with the C compiler (CC78K4). * R/W ..................................... Indicates whether the SFR is read-only, write-only, or read/write. R/W : Read/write R W * Bit units for manipulation .... : Read-only : Write-only
Bit units in which the value of the SFR can be manipulated. SFRs that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. To specify the address of this SFR, describe an even address. SFRs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction.
* After reset ...........................
Indicates the status of the register when the RESET signal has been input.
21
PD784031Y
Table 6-1. Special Function Registers (SFRs) (1/4)
AddressNote Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 bit 0FF00H 0FF01H 0FF02H 0FF03H 0FF06H 0FF07H 0FF0EH 0FF0FH 0FF10H 0FF12H 0FF14H 0FF15H 0FF16H 0FF17H 0FF18H 0FF19H 0FF1AH 0FF1BH 0FF1CH 0FF1DH 0FF20H 0FF21H 0FF23H 0FF26H 0FF27H 0FF2EH 0FF30H 0FF31H 0FF32H 0FF33H Port 0 buffer register H Compare register (timer/counter 0) Capture/compare register (timer/counter 0) Compare register L (timer/counter 1) Compare register H (timer/counter 1) Capture/compare register L (timer/counter 1) Capture/compare register H (timer/counter 1) Compare register L (timer/counter 2) Compare register H (timer/counter 2) Capture/compare register L (timer/counter 2) Capture/compare register H (timer/counter 2) Compare register L (timer 3) Compare register H (timer 3) Port 0 mode register Port 1 mode register Port 3 mode register Port 6 mode register Port 7 mode register Real-time output port control register Capture/compare control register 0 Timer output control register Capture/compare control register 1 Capture/compare control register 2 Port 0 Port 1 Port 2 Port 3 Port 6 Port 7 Port 0 buffer register L P0 P1 P2 P3 P6 P7 P0L P0H CR00 CR01 CR10 CR10W - CR11 CR11W - CR20 CR20W - CR21 CR21W - CR30 CR30W - PM0 PM1 PM3 PM6 PM7 RTPC CRC0 TOC CRC1 CRC2 R R/W R/W - - - - - - - - - - - - - - - 8 bits - - - - - - - - - - - - - - - - - 10H 00H 10H 00H FFH 16 bits - - - - - - - - 00H Undefined Undefined After Reset
Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, "F0000H" is added to this value.
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PD784031Y
Table 6-1. Special Function Registers (SFRs) (2/4)
AddressNote 1 Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 bit 0FF36H 0FF38H 0FF39H 0FF3AH 0FF3BH 0FF41H 0FF43H 0FF4EH 0FF50H 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF5CH 0FF5DH 0FF5EH 0FF5FH 0FF60H 0FF61H 0FF62H 0FF68H 0FF6AH 0FF70H 0FF71H 0FF72H 0FF74H 0FF7DH 0FF80H 0FF81H 0FF82H 0FF83H Prescaler mode register 0 Timer control register 0 Prescaler mode register 1 Timer control register 1 D/A conversion value setting register 0 D/A conversion value setting register 1 D/A converter mode register A/D converter mode register A/D conversion result register PWM control register PWM prescaler register PWM modulo register 0 PWM modulo register 1 One-shot pulse output control register I2C bus control register Timer register 3 Timer register 2 Timer register 1 TM1 - TM2 - TM3 - PRM0 TMC0 PRM1 TMC1 DACS0 DACS1 DAM ADM ADCR PWMC PWPR PWM0 PWM1 OSPC IICC SPRM CSIM SVA R/WNote 2 R R/W R/W TM3W TM2W TM1W Capture register (timer/counter 0) Capture register L (timer/counter 1) Capture register H (timer/counter 1) Capture register L (timer/counter 2) Capture register H (timer/counter 2) Port 1 mode control register Port 3 mode control register Pull-up resistor option register Timer register 0 CR02 CR12 CR12W - CR22 CR22W - PMC1 PMC3 PUO TM0 R R/W R - - - - - - - - - - - - - - - - - - - - - - Note 3 8 bits - - - - - - - - - - - - - - - - - - - - - - - - - - 04H 00H 01H 00H 03H 00H Undefined 05H 00H Undefined 11H 00H 11H 00H - - - 0000H 00H 16 bits 0000H After Reset
Prescaler mode register for serial clock Clocked serial interface mode register Slave address register
Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, "F0000H" is added to this value. 2. Bit 0 is read-only. 3. Only bit 0 can be manipulated in bit units. 23
PD784031Y
Table 6-1. Special Function Registers (SFRs) (3/4)
AddressNote 1 Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 bit 0FF84H 0FF85H 0FF86H 0FF88H 0FF89H 0FF8AH 0FF8BH 0FF8CH Clocked serial interface mode register 1 Clocked serial interface mode register 2 Serial shift register Asynchronous serial interface mode register Asynchronous serial interface mode register 2 Asynchronous serial interface status register Asynchronous serial interface status register 2 Serial receive buffer: UART0 Serial transmit shift register: UART0 Serial shift register: IOE1 0FF8DH Serial receive buffer: UART2 Serial transmit shift register: UART2 Serial shift register: IOE2 0FF90H 0FF91H 0FFA0H 0FFA1H 0FFA4H 0FFA8H 0FFAAH 0FFACH 0FFADH 0FFAEH 0FFC0H 0FFC2H 0FFC4H 0FFC5H 0FFC6H 0FFC7H 0FFC8H Baud rate generator control register Baud rate generator control register 2 External interrupt mode register 0 External interrupt mode register 1 Sampling clock select register In-service priority register Interrupt mode control register Interrupt mask register 0L Interrupt mask register 0H Interrupt mask register 1L Standby control register Watchdog timer mode register Memory expansion mode register Hold mode register Clock output mode register Programmable wait control register 1 Programmable wait control register 2 CSIM1 CSIM2 SIO ASIM ASIM2 ASIS ASIS2 RXB TXS SIO1 RXB2 TXS2 SIO2 BRGC BRGC2 INTM0 INTM1 SCS0 ISPR IMC MK0L MK0 MK0H MK1L STBC WDM MM HLDM CLOM PWC1 PWC2 R R/W W R/W R W R/W R R/W - - - - - - - - - - - - - - 8 bits Note 2 Note 2 - - - - - - - - AAH AAAAH FFH 30H 00H 20H 00H 16 bits - - - - - - - - - - - - - - - - - - - - 80H FFFFH 00H Undefined 00H After Reset
Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, "F0000H" is added to this value. 2. Data can be written by using only dedicated instructions such as MOV STBC, #byte and MOV WDM, #byte, and cannot be written with any other instructions.
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PD784031Y
Table 6-1. Special Function Registers (SFRs) (4/4)
AddressNote Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 bit 0FFCCH 0FFCDH 0FFCFH Refresh mode register Refresh area specification register Oscillation stabilization time specification register 0FFD0H to 0FFDFH 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE7H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFECH 0FFEDH 0FFEEH 0FFEFH Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTC00) Interrupt control register (INTC01) Interrupt control register (INTC10) Interrupt control register (INTC11) Interrupt control register (INTC20) Interrupt control register (INTC21) Interrupt control register (INTC30) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTAD) Interrupt control register (INTSER) Interrupt control register (INTSR) Interrupt control register (INTCSI1) 0FFF0H 0FFF1H 0FFF2H 0FFF3H Interrupt control register (INTST) Interrupt control register (INTCSI) Interrupt control register (INTSER2) Interrupt control register (INTSR2) Interrupt control register (INTCSI2) 0FFF4H 0FFF5H Interrupt control register (INTST2) Interrupt control register (INTSPC) PIC0 PIC1 PIC2 PIC3 CIC00 CIC01 CIC10 CIC11 CIC20 CIC21 CIC30 PIC4 PIC5 ADIC SERIC SRIC CSIIC1 STIC CSIIC SERIC2 SRIC2 CSIIC2 STIC2 SPCIC - - - - - - - - - - - - - - - - - - - - - - - - 43H External SFR area - - - RFM RFA OSTS R/W - 8 bits 16 bits - - - 00H After Reset
Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, "F0000H" is added to this value.
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PD784031Y
7. PERIPHERAL HARDWARE FUNCTIONS 7.1 Ports
The ports shown in Figure 7-1 are provided to make various control operations possible. Table 7-1 shows the function of each port. Ports 0 through 6 can be connected to internal pull-up resistors by software when inputting. Figure 7-1. Port Configuration
P00 Port 0 P07 P10 Port 1 P17
P20 to P27
8
Port 2
P30 Port 3 P37 P60 P63 P66 P67 P70 Port 6
Port 7 P77
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PD784031Y
Table 7-1. Port Functions
Port Name Pin Name Function Specification of Pull-up Resistor Connection by Software Port 0 P00 to P07 * Can be set in input or output mode in 1-bit units. * Can operate as 4-bit real-time output port (P00 through P03 and P04 through P07). * Can drive transistor. Port 1 P10 to P17 * Can be set in input or output mode in 1-bit units. * Can drive LEDs. Port 2 Port 3 Port 6 P20 to P27 P30 to P37 P60 to P63 P66, P67 Port 7 P70 to P77 * Input port * Can be set in input or output mode in 1-bit units. * Output only * Can be set in input or output mode in 1-bit units. * Can be set in input or output mode in 1-bit units. - In 6-bit units (P22 through P27) All port pins in input mode All port pins in input mode All port pins in input mode All port pins in input mode
7.2 Clock Generation Circuit
An on-chip clock generation circuit necessary for operation is provided. This clock generation circuit has a divider circuit. If high-speed operation is not necessary, the internal operating frequency can be lowered by the divider circuit to reduce the current consumption. Figure 7-2. Block Diagram of Clock Generation Circuit
X1 Oscillation circuit X2
fXX 1/2 1/2 1/2 1/2
Selector
fCLK CPU Peripheral circuit
fXX/2 UART/IOE INTP0 noise reduction circuit Oscillation stabilization timer
Remark fXX : oscillation frequency or external clock input fCLK: internal operating frequency
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PD784031Y
Figure 7-3. Example of Using Oscillation Circuit (1) Crystal/ceramic oscillation
PD784031Y
VSS1 X1
X2
(2) External clock * EXTC bit of OSTS = 1 * EXTC bit of OSTS = 0
PD784031Y
X1
PD784031Y
X1
PD74HC04, etc.
X2
Open
X2
Caution
When using the clock oscillation circuit, wire the dotted portion in the above figure as follows to avoid adverse influences of wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the potential at the ground point of the capacitor in the oscillation circuit the same as VSS1. Do not ground to a ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit.
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PD784031Y
7.3 Real-time Output Port
The real-time output port outputs data stored in a buffer in synchronization with the coincidence interrupt generated by timer/counter 1 or with an external interrupt. As a result, pulses without jitter can be output. The real-time output port is therefore ideal for applications where arbitrary patterns must be output at specific intervals (such as open loop control of a stepping motor). The real-time output port mainly consists of port 0 and port 0 buffer registers (P0H and P0L) as shown in Figure 7-4. Figure 7-4. Block Diagram of Real-time Output Port
Internal bus
8
4
4
Real-time output port control register (RTPC)
Buffer register 8 P0H P0L
INTP0 (from external source) INTC10 (from timer/counter 1) INTC11 (from timer/counter 1) Output trigger control circuit
4
4
Output latch (P0)
P07
P00
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PD784031Y
7.4 Timer/Counter
Three units of timers/counters and one unit of timer are provided. Because a total of seven interrupt requests are supported, these timers/counters and timer can be used as seven units of timers/counters. Table 7-2. Operations of Timers/Counters
Name Item Count width 8 bits 16 bits Operation mode Interval timer External event counter One-shot timer Function Timer output Toggle output PWM/PPG output One-shot pulse outputNote Real-time output Pulse width measurement Number of interrupt requests - 2ch - 2ch - 1 input 2 2ch - - - - - 1 input 2 2ch 2ch - - 2 inputs 2 1ch - - - - - - - - 1 Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer 3
Note The one-shot pulse output function makes a pulse output level active by software and inactive by hardware (interrupt request signal). This function is different in nature from the one-shot timer function of timer/counter 2.
30
PD784031Y
Figure 7-5. Block Diagram of Timers/Counters Timer/counter 0
Clear control
Selector
Software trigger
fXX/8
Prescaler
Timer register 0 (TM0)
OVF
Compare register (CR01)
Match
Pulse output control
Compare register (CR00)
Match
TO0
TO1
INTP3
Edge detection INTP3
Capture register (CR02)
INTC00 INTC01
Timer/counter 1
Clear control
Selector
fXX/8
Prescaler
Timer register 1 (TM1/TM1W)
OVF
Event input
Compare register (CR10/CR10W)
Match
INTC10 To real-time output port
INTP0
Edge detection INTP0
Capture/Compare register (CR11/CR11W)
Match
INTC11
Capture register (CR12/CR12W)
Timer/counter 2
Clear control
Selector
fXX/8
Prescaler
Timer register 2 (TM2/TM2W)
OVF
INTP2/CI
Edge detection INTP2
Capture/Compare register (CR21/CR21W)
Match
Pulse output control
Compare register (CR20/CR20W)
Match
TO2
TO3
INTP1
Edge detection INTP1
Capture register (CR22/CR22W)
INTC20 INTC21
Timer 3
fXX/8 Prescaler Timer register 3 (TM3/TM3W) Clear
Compare register (CR30/CR30W)
Match
CSI
INTC30
Remark OVF: overflow flag
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PD784031Y
7.5 PWM Output (PWM0, PWM1)
Two channels of PWM (pulse width modulation) output circuits with a resolution of 12 bits and a repeat frequency of 62.5 kHz (fCLK = 16 MHz) are provided. Both these PWM output channels can select a high or low level as the active level. These outputs are ideal for controlling the speed of a DC motor. Figure 7-6. Block Diagram of PWM Output Unit
Internal bus 16 PWM modulo register PWMn 15 8 87 43 0 8 PWM control register (PWMC)
4 Reload control
fCLK
Prescaler
8-bit down counter
Pulse control circuit 4-bit counter
Output control
PWMn (output pin)
1/256
Remark n = 0 or 1
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PD784031Y
7.6 A/D Converter
An analog-to-digital (A/D) converter with eight multiplexed inputs (ANI0 through ANI7) is provided. This A/D converter is of successive approximation type. The result of conversion is retained by an 8-bit A/D conversion result register (ADCR). Therefore, high-speed, high-accuracy conversion can be performed (conversion time: approx. 7.5
s at fCLK = 16 MHz).
A/D conversion can be started in either of the following two modes: * Hardware start: Conversion is started by trigger input (INTP5). * Software start: Conversion is started by setting a bit of the A/D converter mode register (ADM). After started, the A/D converter operates in the following modes: * Scan mode: Two or more analog inputs are sequentially selected, and data to be converted are obtained from all the input pins. * Select mode: Only one analog input pin is used to continuously obtain converted values. These operation modes and whether starting or stopping the A/D converter are specified by the ADM. When the result of conversion is transferred to the ADCR, interrupt request INTAD is generated. By using this request and macro service, the converted values can be successively transferred to the memory. Figure 7-7. Block Diagram of A/D Converter
Successive approximation register (SAR) Edge detection circuit Conversion trigger INTAD
INTP5
Control Circuit
Tap selector
ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7
Input selector
Sample & hold circuit
Series resistor string AVREF1 R/2 Voltage comparator R
R/2 AVSS
Trigger enable 8 A/D converter mode register (ADM) A/D conversion result register (ADCR)
8
8
Internal bus
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PD784031Y
7.7 D/A Converter
Two circuits of digital-to-analog (D/A) converters are provided. These D/A converters are of voltage output type and have a resolution of 8 bits. The conversion method is of R-2R resistor ladder type. By writing a value to be output to an 8-bit D/A conversion value setting register (DACSn: n = 0 or 1), an analog value is output to the ANOn (n = 0 or 1) pin. The output voltage range is determined by the voltage applied across the AVREF2 and AVREF3 pins. Because the output impedance is high, no current can be extracted from the output. If the impedance of the load is low, insert a buffer amplifier between the load and output pin. The ANOn pin goes into a high-impedance state while the RESET signal is low. After releasing reset, DACSn is cleared to 0. Figure 7-8. Block Diagram of D/A Converter
ANOn 2R AVREF2 R
2R
Selector
R
2R AVREF3 R
2R
DACSn
DACEn
Internal bus
Remark n = 0 or 1
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PD784031Y
7.8 Serial Interface
Three independent serial interface channels are provided. Asynchronous serial interface (UART)/3-wire serial I/O (IOE) x 2 Clocked serial interface (CSI) x 1 * 3-wire serial I/O (IOE) * 2-wire serial I/O (IOE) * I2C bus interface (I2C) Therefore, communication with an external system and local communication within the system can be simultaneously executed (refer to Figure 7-9). Figure 7-9. Example of Serial Interface (a) UART + I2C
PD784031Y (master)
PD4711A
[UART] RxD RS-232-C driver/receiver TxD Port SDA SCL [I2C] SDA SCL VDD VDD
PD6272 (EEPROMTM)
PD78062Y (slave)
SDA LCD
PD4711A
[UART] RxD2 RS-232-C driver/receiver TxD2 Port
SCL
(b) UART + 3-wire serial I/O + 2-wire serial I/O
PD784031Y (master)
PD4711A
[UART] RxD RS-232-C driver/receiver TxD Port SO1 SI1 SCK1 INTPm Port VDD VDD Note [3-wire serial I/O]
PD75108 (slave)
SI SO SCK Port INT
PD78014 (slave)
SDA SCL INTPn Port [2-wire serial I/O] Note SB0 SCK0 Port INT
Note Handshake line
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PD784031Y
7.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) Two channels of serial interfaces that can select an asynchronous serial interface mode and 3-wire serial I/O mode are provided. (1) Asynchronous serial interface mode In this mode, data of 1 byte following the start bit is transferred or received. Because an on-chip baud rate generator is provided, a wide range of baud rates can be set. Moreover, the clock input to the ASCK pin can be divided to define a baud rate. When the baud rate generator is used, a baud rate conforming to the MIDI standard (31.25 kbps) can be also obtained. Figure 7-10. Block Diagram in Asynchronous Serial Interface Mode
Internal bus
Receive buffer
RXB, RXB2
RXD, RXD2
Receive shift register
Transmit shift register
TXS, TXS2
TXD, TXD2
Receive control parity check
INTSR, INTSR2 INTSER, INTSER2
Transmit control parity append
INTST, INTST2
Baud rate generator
1/2m fXX/2 ASCK, ASCK2
Selector
1/2n + 1 1/2m
Remark fXX: oscillation frequency or external clock input n = 0 through 11 m = 16 through 30
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PD784031Y
(2) 3-wire serial I/O mode In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in synchronization with this clock. This mode is used to communicate with a device having the conventional clocked serial interface. Basically, communication is established by using three lines: one serial clock (SCK) and two serial data (SI and SO) lines. Generally, to check the communication status, a handshake line is necessary. Figure 7-11. Block Diagram in 3-wire Serial I/O Mode
Internal bus
Direction control circuit
SIO1, SIO2 SI1, SI2 Shift register Output latch
SO1, SO2
SCK1, SCK2
Serial clock counter
Interrupt signal generation circuit
INTCSI1, INTCSI2
Selector
1/m
1/2n + 1
fXX/2
Serial clock control circuit
Remark fXX: oscillation frequency or external clock input n = 0 through 11 m = 1 or 16 through 30
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PD784031Y
7.8.2 Clocked serial interface (CSI) In this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data in synchronization with this clock. Figure 7-12. Block Diagram of Clocked Serial Interface
Internal bus
Direction control register
Slave address register Match signal
SI0 Selector SO0/SDA Shift register
Set Output latch
Reset
N-ch open drain output (in 2-wire or I2C bus mode)
Start condition detection circuit Acknowledge detection circuit
Acknowledge detection control
Wake-up control circuit
Stop condition detection circuit
INTSPC
SCK0/SCL
Serial clock counter
Interrupt signal generation circuit
INTCSI
Serial clock control circuit Selector N-ch open drain output (in 2-wire or I2C bus mode) CLS0 CLS1
Timer 3 output fXX/16
Selector
Prescaler
fXX/2
Remark fXX: oscillation frequency or external clock input
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PD784031Y
(1) 3-wire serial I/O mode This mode is to communicate with devices having the conventional clocked serial interface. Basically, communication is established in this mode with three lines: one serial clock (SCK0) and two serial data (SI0 and SO0) lines. Generally, a handshake line is necessary to check the communication status. (2) 2-wire serial I/O mode This mode is to transfer 8-bit data by using two lines: serial clock (SCL) and serial data bus (SDA). Generally, a handshake line is necessary to check the communication status. (3) I2C (Inter IC) bus mode This mode is to communicate with devices conforming to the I2C bus format. This mode is to transfer 8-bit data with two or more devices by using two lines: serial clock (SCL) and serial data bus (SDA). During transfer, a "start condition", "data", and "stop condition" can be output onto the serial data bus. During reception, these data can be automatically detected by hardware.
7.9 Edge Detection Function
The interrupt input pins (NMI and INTP0 through INTP5) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. Because these pins operate at an edge of the input signal, they have a function to detect an edge. Moreover, a noise reduction circuit is also provided to prevent erroneous detection due to noise. Pin Name NMI INTP0 to INTP3 INTP4, INTP5 Detectable Edge Either of rising or falling edge Either or both of rising and falling edges Noise Reduction By analog delay By clock samplingNote By analog delay
Note
INTP0 can select a sampling clock.
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PD784031Y
7.10 Watchdog Timer
A watchdog timer is provided to detect a hang up of the CPU. This watchdog timer generates a non-maskable interrupt unless it is cleared by software within a specified interval time. Once enabled to operate, the watchdog timer cannot be stopped by software. Whether the interrupt by the watchdog timer or the interrupt input from the NMI pin takes precedence can be specified. Figure 7-13. Block Diagram of Watchdog Timer
fCLK
Timer
fCLK/221 fCLK/220 fCLK/219 fCLK/217
Selector
INTWDT
Clear signal
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PD784031Y
8. INTERRUPT FUNCTION
As the servicing in response to an interrupt request, the three types shown in Table 8-1 can be selected by program. Table 8-1. Servicing of Interrupt Request
Servicing Mode Vector interrupt Entity of Servicing Software Servicing Branches and executes servicing routine (servicing is arbitrary). Context switching Automatically switches register bank, branches and executes servicing routine (servicing is arbitrary). Macro service Firmware Executes data transfer between memory and I/O (servicing is fixed). Retained Contents of PC and PSW Saves to and restores from stack. Saves to or restores from fixed area in register bank.
8.1 Interrupt Sources
Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 24 types of sources, execution of the BRK instruction or BRKCS instruction, or an operand error. The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt servicing and that which of the two or more interrupts that simultaneously occur should be serviced first. When the macro service function is used, however, nesting always proceeds. The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having the same request, simultaneously generate (refer to Table 8-2).
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PD784031Y
Table 8-2. Interrupt Sources
Type Software Default Priority - Name BRK instruction BRKCS instruction Operand error If result of exclusive OR between byte of operand and byte is not FFH when MOV STBC, #byte, MOV WDM, #byte, or LOCATION instruction is executed Detection of pin input edge Overflow of watchdog timer Detection of pin input edge (TM1/TM1W capture trigger, TM1/TM1W event counter input) Detection of pin input edge (TM2/TM2W capture trigger, TM2/TM2W event counter input) Detection of pin input edge (TM2/TM2W capture trigger, TM2/TM2W event counter input) Detection of pin input edge (TM0 capture trigger, TM0 event counter input) Generation of TM0-CR00 match signal Generation of TM0-CR01 match signal Generation of TM1-CR10 match signal (in 8-bit operation mode) Generation of TM1W-CR10W match signal (in 16-bit operation mode) Generation of TM1-CR11 match signal (in 8-bit operation mode) Generation of TM1W-CR11W match signal (in 16-bit operation mode) Generation of TM2-CR20 match signal (in 8-bit operation mode) Generation of TM2W-CR20W match signal (in 16-bit operation mode) Generation of TM2-CR21 match signal (in 8-bit operation mode) Generation of TM2W-CR21W match signal (in 16-bit operation mode) Generation of TM3-CR30 match signal (in 8-bit operation mode) Generation of TM3W-CR30W match signal (in 16-bit operation mode) Detection of pin input edge Detection of pin input edge End of A/D conversion (transfer of ADCR) Occurrence of ASI0 reception error End of ASI0 reception or CSI1 transfer End of ASI0 transfer End of CSI1 transfer Occurrence of ASI2 reception error End of ASI2 reception or CSI2 transfer End of ASI2 transfer I2C bus stop condition interrupt - Internal - External Internal External Internal External - Instruction execution Source Trigger Internal/ External - - Macro Service
Non-maskable Maskable
- 0 (highest) 1 2 3 4 5 6
NMI WDT INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10
7
INTC11
8
INTC20
9
INTC21
10
INTC30
11 12 13 14 15 16 17 18 19 20 21 (lowest)
INTP4 INTP5 INTAD INTSER INTSR INTCSI1 INTST INTCSI INTSER2 INTSR2 INTCSI2 INTST2 INTSPC
Remark ASI: asynchronous serial interface CSI: clocked serial interface 42
PD784031Y
8.2 Vectored Interrupt
Execution branches to a servicing routing by using the memory contents of a vector table address corresponding to the interrupt source as the address of the branch destination. So that the CPU performs interrupt servicing, the following operations are performed: * On branching : Saves the status of the CPU (contents of PC and PSW) to stack * On returning : Restores the status of the CPU (contents of PC and PSW) from stack To return to the main routine from an interrupt service routine, the RETI instruction is used. The branch destination address is in a range of 0 to FFFFH. Table 8-3. Vector Table Address Interrupt Source BRK instruction Operand error NMI WDT INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11 INTC20 INTC21 INTC30 INTP4 INTP5 INTAD INTSER INTSR INTCSI1 INTST INTCSI INTSER2 INTSR2 INTCSI2 INTST2 INTSPC 002EH 0030H 0026H 0028H 002AH 002CH Vector Table Address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H
43
PD784031Y
8.3 Context Switching
When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register bank is selected by hardware. Context switching is a function that branches execution to a vector address stored in advance in the register bank, and to stack the current contents of the program counter (PC) and program status word (PSW) to the register bank. The branch address is in a range of 0 to FFFFH. Figure 8-1. Context Switching Operation when Interrupt Request is Generated
0000B <7> Transfer Register bank n (n = 0 to 7) PC19 to 16 PC15 to 0 A B <2> Save (bits 8 through 11 of temporary register) <6> Exchange R5 R7 <5> Save V U Temporary register <1> Save T W D H VP UP E L X C R4 R6
Register bank n (0 to 7)
<3> Switching of register bank (RBS0 to RBS2 n) <4> RSS 0 IE 0
PSW
8.4 Macro Service
This function is to transfer data between memory and a special function register (SFR) without intervention by the CPU. A macro service controller accesses the memory and SFR in the same transfer cycle and directly transfers data without loading it. Because this function does not save or restore the status of the CPU, or load data, data can be transferred at high speeds. Figure 8-2. Macro Service
Read CPU Memory Write Macro service controller
Write SFR Read
Internal bus
44
PD784031Y
8.5 Application Example of Macro Service
(1) Transfer of serial interface
Transfer data storage buffer (memory) Data n Data n - 1
Data 2 Data 1
Internal bus
TxD
Transfer shift register TXS (SFR)
Transfer control
INTST
Each time macro service request INTST is generated, the next transfer data is transferred from memory to TXS. When data n (last byte) has been transferred to TXS (when the transfer data storage buffer has become empty), vectored interrupt request INTST is generated. (2) Reception of serial interface
Receive data storage buffer (memory) Data n Data n - 1
Data 2 Data 1
Internal bus
Receive buffer
RXB (SFR)
RxD
Receive shift register
Reception control
INTSR
Each time macro service request INTSR is generated, the receive data is transferred from RXB to memory. When data n (last byte) has been transferred to memory (when the receive data storage buffer has become full), vectored interrupt request INTSR is generated.
45
PD784031Y
(3) Real-time output port INTC10 and INTC11 serve as the output triggers of the real-time output port. The macro services for these can set the following output pattern and intervals simultaneously. Therefore, INTC10 and INTC11 can control two stepping motors independently of each other. They can also be used for PWM output or to control DC motors.
Output pattern profile (memory) Pn Pn - 1
Output timing profile (memory) Tn Tn - 1
P2 P1
T2 T1
Internal bus
Internal bus
Match (SFR) P0L INTC10 Output latch P00 to P03 TM1 CR10 (SFR)
Each time macro service request INTC10 is generated, the pattern and timing are transferred to the buffer register (P0L) and compare register (CR10), respectively. When the contents of the timer register 1 (TM1) coincide with those of CR10, INTC10 is generated again, and the contents of P0L are transferred to the output latch. When Tn (last byte) has transferred to CR10, vectored interrupt request INTC10 is generated. The same applies to INTC11.
46
PD784031Y
9. LOCAL BUS INTERFACE
The local bus interface can connect an external memory or I/O (memory mapped I/O) and support a memory space of 1 Mbytes (refer to Figure 9-1). Figure 9-1. Example of Local Bus Interface
PD784031Y
A16 to A19
RD WR REFRQ Pseudo SRAM PROM PD27C1001A
Decoder
Character generator PD24C1000
AD0 to AD7
Data bus
ASTB
Latch
A8 to A15
Address bus
Gate array I/O expansion Centronics I/F, etc.
9.1 Memory Expansion
The memory capacity can be expanded in seven steps, from 256 bytes to 1 Mbytes, by connecting an external program memory and data memory.
47
PD784031Y
9.2 Memory Space
The 1-Mbyte memory space is divided into eight spaces of logical addresses. Each space can be controlled by using the programmable wait function and pseudo static RAM refresh function. Figure 9-2. Memory Space
F F F F FH
512 Kbytes
8 0 0 0 0H 7 F F F FH
256 Kbytes 4 0 0 0 0H 3 F F F FH 128 Kbytes 2 0 0 0 0H 1 F F F FH 64 Kbytes 1 0 0 0 0H 0 F F F FH 16 Kbytes 0C0 0 0H 0 BF F FH 16 Kbytes 0 8 0 0 0H 0 7 F F FH 16 Kbytes 0 4 0 0 0H 0 3 F F FH 16 Kbytes 0 0 0 0 0H
48
PD784031Y
9.3 Programmable Wait
The memory space can be divided into eight spaces and wait states can be independently inserted in each of these spaces while the RD and WR signals are active. Even when a memory with a different access time is connected, therefore, the efficiency of the entire system does not drop. In addition, an address wait function that extends the active period of the ASTB signal is also provided so as to have a sufficient address decode time (this function can be set to the entire space).
9.4 Pseudo Static RAM Refresh Function
The following refresh operations can be performed: * Pulse refresh : A bus cycle that outputs a refresh pulse to the REFRQ pin at a fixed cycle is inserted. The memory spaces is divided into eight spaces, and a refresh pulse can be output from the REFRQ pin while a specified memory space is accessed. Therefore, the normal memory access is not kept to wait by the refresh cycle. * Power-down self-refresh : The low level is output to the REFRQ pin in the standby mode to retain the contents of the pseudo static RAM.
9.5 Bus Hold Function
A bus hold function is provided to facilitate connection of a DMA controller. When a bus hold request signal (HLDRQ) is received from an external bus master, the address bus, address/data bus, and ASTB, RD, and WR pins go into a highimpedance state when the current bus cycle has been completed. This makes the bus hold acknowledge (HLDAK) signal active, and releases the bus to the external bus master. Note that, while the bus hold function is used, the external wait function and pseudo static RAM refresh function cannot be used.
49
PD784031Y
10. STANDBY FUNCTION
This function is to reduce the power dissipation of the chip, and can be used in the following modes: * HALT mode : Stops supply of the operating clock to the CPU. This mode is used in combination with the normal operation mode for intermittent operation to reduce the average power dissipation. * IDLE mode : Stops the entire system with the oscillation circuit continuing operation. The power dissipation in this mode is close to that in the STOP mode. However, the time required to restore the normal program operation from this mode is almost the same as that from the HALT mode. * STOP mode : Stops the oscillator and thereby to stop all the internal operations of the chip. Consequently, the power dissipation is minimized with only leakage current flowing. These modes are programmable. The macro service can be started from the HALT mode. Figure 10-1. Transition of Standby Status
n ilizatio n stab Program cillatio xpires Os operation Waits for time e oscillation stabilization
1 te No
te 1
Macro service request End of one processing End of macro service
Macro service
IN
TP
de mo ut np ST Ti ts Se ESE R OP
NM
STOP (standby)
IDLE (standby)
NM
Interrupt request of masked interrupt
HALT (standby)
Notes 1. When INTP4 and INTP5 are not masked 2. Only interrupt requests that are not masked Remark Only the externally input NMI is valid. The watchdog timer cannot be used to release the standby mode (STOP/ IDLE mode).
50
M a En cro s d of erv on ice e pr req oc u es est sin g
N t es qu re put e pt in od ru m ET er Int RES ALT H ts
ts ID R L TP ESE E m o 4, T IN inp de TP u 5t inp ut N o
ut
Se
IN
TP
5
inp
Se
ot
4,
e2
I,
I,
IN
PD784031Y
11. RESET FUNCTION
When the low level is input to the RESET pin, the internal hardware is initialized (reset status). When the RESET pin goes high, the following data are set to the program counter (PC). * Lower 8 bits of PC : contents of address 0000H * Middle 8 bits of PC : contents of address 0001H * Higher 4 bits of PC : 0 Program execution is started from a branch destination address which is the contents of the PC. Therefore, the system can be reset and started from any address. Set the contents of each register by program as necessary. The RESET input circuit has a noise reduction circuit to prevent malfunctioning due to noise. This noise reduction circuit is a sampling circuit by analog delay. Figure 11-1. Accepting Reset Signal
Delay Delay Delay Initialize PC Executes instruction at reset start address
RESET (input)
Internal reset signal
Reset starts
Reset ends
Assert the RESET signal active until the oscillation stabilization time (approx. 40 ms) elapses to execute a power-ON reset operation. Figure 11-2. Power-ON Reset Operation
Oscillation stabilization time Delay Initialize PC Executes instruction at reset start address
VDD
RESET (input)
Internal reset signal
Reset ends
51
PD784031Y
12. INSTRUCTION SET
(1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHIKL, CHKLA Table 12-1. Instruction List by 8-bit Addressing
Second Operand #byte A r r' First Operand A (MOV) ADDNote 1 (MOV) (XCH) MOV XCH (MOV)Note 6 (XCH)Note 6 MOV (XCH) (MOV) (XCH) saddr saddr' sfr !addr16 !!addr24 mem [saddrp] [%saddrg] MOV XCH ADDNote 1 r3 PSWL PSWH MOV (MOV) (XCH) (ADD)Note 1 RORNote 3 MULU DIVUW INC DEC saddr MOV ADDNote 1 (MOV)Note 6 MOV MOV XCH ADDNote 1 sfr MOV MOV MOV INC DEC DBNZ PUSH POP CHKL CHKLA !addr16 !!addr24 mem [saddrp] [%saddrg] mem3 ROR4 ROL4 r3 PSWL PSWH B, C STBC, WDM [TDE+] [TDE-] MOV (MOV) (ADD)Note 1 MOVMNote 4 MOVBKNote 5 DBNZ MOV MOV MOV (MOV) ADDNote 1 MOV ADDNote 1 MOV [WHL+] [WHL-] n NoneNote 2
(ADD)Note 1 (ADD)Note 1 (ADD)Note 1,6 (ADD)Note 1 ADDNote 1 r MOV ADDNote 1 (MOV) (XCH) MOV XCH MOV XCH MOV XCH MOV XCH
(ADD)Note 1 ADDNote 1 ADDNote 1 ADDNote 1
(ADD)Note 1 ADDNote 1
ADDNote 1 (ADD)Note 1 ADDNote 1
Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR. 4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as that of MOVM. 5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of MOVBK. 6. The code length of some instructions having saddr2 as saddr in this combination is short.
52
PD784031Y
(2) 16-bit instructions (The instructions in parentheses are combinations realized by describing AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instruction List by 16-bit Addressing
Second Operand #word AX rp rp' First Operand AX (MOVW) ADDWNote 1 (MOVW) (XCHW) (ADD)Note 1 rp MOVW ADDWNote 1 (MOVW) (XCHW) (MOVW) (MOVW)Note 3 MOVW (MOVW) XCHW saddrp saddrp' sfrp !addr16 !!addr24 mem [saddrp] [%saddrg] MOVW XCHW (MOVW) (XCHW) [WHL+] byte n NoneNote 2
(XCHW) (XCHW)Note 3 (XCHW) (ADDW)Note 1 MOVW XCHW (ADDW)Note 1,3 MOVW XCHW (ADDW)Note 1 MOVW XCHW
MOVW
SHRW SHLW
MULWNote 4 INCW DECW INCW DECW
(ADDW)Note 1 ADDWNote 1 ADDWNote 1 ADDWNote 1 saddrp MOVW (MOVW)Note 3 MOVW MOVW XCHW ADDWNote 1 sfrp MOVW ADDWNote 1 !addr16 !!addr24 mem [saddrp] [%saddrg] PSW MOVW MOVW MOVW (ADDW)Note 1 (MOVW) MOVW ADDWNote 1 MOVW MOVTBLW
ADDWNote 1 (ADDW)Note 1 ADDWNote 1
PUSH POP
PUSH POP
SP
ADDWG SUBWG
post
PUSH POP PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes 1. The operands of SUBW and CMPW are the same as that of ADDW. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The code length of some instructions having saddrp2 as saddrp in this combination is short. 4. The operands of MULUW and DIVUX are the same as that of MULW.
53
PD784031Y
(3) 24-bit instructions (The instructions in parentheses are combinations realized by describing WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 12-3. Instruction List by 24-bit Addressing
Second Operand #imm24 WHL rg rg' First Operand WHL (MOVG) (ADDG) (SUBG) rg MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH POP saddrg !!addr24 mem1 [%saddrg] SP MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] SP NoneNote
Note Either the second operand is not used, or the second operand is not an operand address.
54
PD784031Y
(4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 12-4. Bit Manipulation Instructions
Second Operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit First Operand CY !addr16.bit !!addr24.bit MOV1 AND1 OR1 XOR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 NOT1 SET1 CLR1 BF BT BTCLR BFSET /saddr.bit /sfr. bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 OR1 NOT1 SET1 CLR1 NoneNote
Note Either the second operand is not used, or the second operand is not an operand address.
55
PD784031Y
(5) Call and return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 12-5. Call and Return/Branch Instructions
Operand of Instruction Address Basic instruction BCNote BR CALL BR CALL BR RETCS RETCSB Compound instruction BF BT BTCLR BFSET DBNZ CALL BR CALL BR CALL BR CALL BR CALL BR CALLF CALLF BRKCS BRK RET RETI RETB $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None
Note The operands of BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS
56
PD784031Y
13. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD AVDD AVSS Input voltage Output voltage Output current low-level VI VO IOL 1 pin Total of output pins Output current high-level IOH 1 pin Total of output pins Reference input voltage to A/D converter Reference input voltage to D/A converter Operating ambient temperature Storage temperature Tstg -65 to +150 C AVREF1 Test Conditions Ratings -0.5 to +7.0 AVSS to VDD + 0.5 -0.5 to +0.5 -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 15 100 -10 -100 -0.5 to VDD + 0.3 Unit V V V V V mA mA mA mA V
AVREF2 AVREF3 TA
-0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -40 to +85
V V C
Caution
The product quality may be damaged even if a value of only one of the above parameters exceeds the absolute maximum rating or any value exceeds the absolute maximum rating for an instant. That is, the absolute maximum rating is a rating value which may cause a product to be damaged physically. The absolute maximum rating values must therefore be observed in using the product.
57
PD784031Y
Operating Condition
* Operating ambient temperature (TA) : -40 to +85C * Rise, fall time (tr, tf) (unspecified pins) : 0 to 200 s * Supply voltage and clock cycle time : refer to Figure 13-1
Figure 13-1. Supply Voltage and Clock Cycle Time
10000 4000
Clock Cycle Time tCYK [ns]
1000
Guaranteed Operation Range
125 100 62.5
10
0
1
2 3 4 5 Supply Voltage [V]
6
7
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Test Conditions f = 1 MHz Unmeasured pins returned to 0 V. MIN. TYP. MAX. 10 10 10 Unit pF pF pF
58
PD784031Y
Oscillator Characteristics (TA = -40 to +85C, VDD = +4.5 to 5.5 V, VSS = 0 V)
Resonator Ceramic resonator or crystal resonator VSS1 X1 X2 Recommended Circuit Parameter Oscillation frequency (fXX) MIN. 4 MAX. 32 Unit MHz
C1
C2
External clock
X1 input frequency (fX)
4
32
MHz
X1
X2
X1 input rise, fall time (tXR, tXF)
0
10
ns
HCMOS inverter
X1 input high-/low-level width (tWXH, tWXL)
10
125
ns
Caution
When using the clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS1. Do not ground it to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator.
59
PD784031Y
Oscillator Characteristics (TA = -40 to +85C, VDD = +2.7 to 5.5 V, VSS = 0 V)
Resonator Ceramic resonator or crystal resonator VSS1 X1 X2 Recommended Circuit Parameter Oscillation frequency (fXX) MIN. 4 MAX. 16 Unit MHz
C1
C2
External clock
X1 input frequency (fX)
4
16
MHz
X1
X2
X1 input rise, fall time (tXR, tXF)
0
10
ns
HCMOS inverter
X1 input high-/low-level width (tWXH, tWXL)
10
125
ns
Caution
When using the clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS1. Do not ground it to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator.
60
PD784031Y
DC Characteristics (TA = -40 to +85C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (1/2)
Parameter Input voltage low-level Symbol VIL1 Test Conditions Except for pins shown in Notes 1, 2, 3, 4, 6 Pins shown in Notes 1, 2, 3, 4, 6 VDD = +5.0 V 10 % Pins shown in Notes 2, 3, 4 Except for pins shown in Notes 1, 6 Pins shown in Notes 1, 6 VDD = +5.0 V 10 % Pins shown in Notes 2, 3, 4 IOL = 2 mA Except for pins shown in Note 6 IOL = 3 mA Pins shown in Note 6 IOL = 6 mA Pins shown in Note 6 VOL3 VDD = +5.0 V 10 % IOL = 8 mA Pins shown in Notes 2, 5 IOH = -2 mA VDD = +5.0 V 10 % IOH = -5 mA Pins shown in Note 4 EXTC = 0 0 V VI VIL2 EXTC = 0 VIH2 VI VDD VDD - 1.0 VDD - 1.4 1.0 V MIN. -0.3 TYP. MAX. 0.3VDD Unit V
VIL2 VIL3
-0.3 -0.3
0.2VDD +0.8
V V
Input voltage high-level
VIH1 VIH2 VIH3
0.7VDD 0.8VDD 2.2
VDD + 0.3 VDD + 0.3 VDD + 0.3
V V V
Output voltage low-level
VOL1
0.4
V
VOL2
0.4
V
0.6
V
Output voltage high-level
VOH1 VOH2
V V
X1 input current low-level
IIL
-30
A A
X1 input current high-level
IIH
+30
Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, TEST 2. AD0 to AD7, A8 to A15 3. P60/A16 to P63/A19, RD, WR, P66/WAIT/HLDRQ, P67/REFRQ/HLDAK 4. P00 to P07 5. P10 to P17 6. P32/SCK0/SCL, P33/SO0/SDA
61
PD784031Y
DC Characteristics (TA = -40 to +85C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (2/2)
Parameter Input leakage current Symbol ILI Test Conditions 0 V VI VDD Except for X1 pin when EXTC = 0 0 V VO VDD Operating mode fXX = 32 MHz VDD = +5.0 V 10 % fXX = 16 MHz VDD = +2.7 to 3.3 V IDD2 HALT mode fXX = 32 MHz VDD = +5.0 V 10 % fXX = 16 MHz VDD = +2.7 to 3.3 V IDD3 IDLE mode (EXTC = 0) fXX = 32 MHz VDD = +5.0 V 10 % fXX = 16 MHz VDD = +2.7 to 3.3 V Pull-up resistor RL VI = 0 V 15 25 MIN. TYP. MAX. 10 10 45 Unit
A A
mA
Output leakage current VDD supply current
ILO IDD1
12
25
mA
13
26
mA
8
12
mA
12
mA
8
mA
80
k
62
PD784031Y
AC Characteristics (TA = -40 to +85C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)
(1) Read/write operation (1/2)
Parameter Address setup time Symbol tSAST Test Conditions VDD = +5.0 V 10 % MIN. (0.5 + a) T - 15 (0.5 + a) T - 31 ASTB high-level width tWSTH VDD = +5.0 V 10 % (0.5 + a) T - 17 (0.5 + a) T - 40 Address hold time (from ASTB) tHSTLA VDD = +5.0 V 10 % 0.5T - 24 0.5T - 34 Address hold time (from RD) Address RD delay time tHRA tDAR VDD = +5.0 V 10 % 0.5T - 14 (1 + a) T - 9 (1 + a) T - 15 Address float time (from RD) Address data input time tFRA tDAID VDD = +5.0 V 10 % 0 (2.5 + a + n) T - 37 (2.5 + a + n) T - 52 ASTB data input time tDSTID VDD = +5.0 V 10 % (2 + n) T - 40 (2 + n) T - 60 RD data input time tDRID VDD = +5.0 V 10 % (1.5 + n) T - 50 (1.5 + n) T - 70 ASTB RD delay time Data hold time (from RD) RD address active time tDSTR tHRID tDRA After program read After data read RD ASTB delay time RD low-level width tDRST tWRL VDD = +5.0 V 10 % VDD = +5.0 V 10 % VDD = +5.0 V 10 % 0.5T - 9 0 0.5T - 8 0.5T - 12 1.5T - 8 1.5T - 12 0.5T - 17 (1.5 + n) T - 30 (1.5 + n) T - 40 Address hold time (from WR) Address WR delay time tHWA tDAW VDD = +5.0 V 10 % 0.5T - 14 (1 + a) T - 5 (1 + a) T - 15 ASTB data output delay time tDSTOD VDD = +5.0 V 10 % 0.5T + 19 0.5T + 35 WR data output delay time ASTB WR output delay time tDWOD tDSTW 0.5T - 9 0.5T - 11 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remark T : TCYK (system clock cycle time) a : 1 in address wait, 0 in the other conditions n : the number of wait (n 0)
63
PD784031Y
(1) Read/write operation (2/2)
Parameter Data setup time (to WR) Symbol tSODW Test Conditions VDD = +5.0 V 10 % MIN. (1.5 + n) T - 30 (1.5 + n) T - 40 Data hold time (from WR)Note tHWOD VDD = +5.0 V 10 % 0.5T - 5 0.5T - 25 WR ASTB delay time WR low-level width tDWST tWWL VDD = +5.0 V 10 % 0.5T - 12 (1.5 + n) T - 30 (1.5 + n) T - 40 MAX. Unit ns ns ns ns ns ns ns
Note The data hold time includes the time to hold VOH1 and VOL1 in the load condition of CL = 50 pF, RL = 4.7 k. Remark T : TCYK (system clock cycle time) n : the number of wait (n 0) (2) Bus hold timing
Parameter HLDRQ float delay time HLDRQ HLDAK delay time Float HLDAK delay time HLDRQ HLDAK delay time HLDAK active delay time tDHAC VDD = +5.0 V 10 % 1T - 20 1T - 30 tDCFHA tDHQLHAL VDD = +5.0 V 10 % Symbol tFHQC tDHQHHAH VDD = +5.0 V 10 % Test Conditions MIN. MAX. (6 + a + n) T + 50 (7 + a + n) T + 30 (7 + a + n) T + 40 1T + 30 2T + 40 2T + 60 Unit ns ns ns ns ns ns ns ns
Remark T : TCYK (system clock cycle time) a : 1 in address wait, 0 in the other conditions n : the number of wait (n 0)
64
PD784031Y
(3) External wait timing
Parameter Address WAIT input time Symbol tDAWT Test Conditions VDD = +5.0 V 10 % MIN. MAX. (2 + a) T - 40 (2 + a) T - 60 ASTB WAIT input time tDSTWT VDD = +5.0 V 10 % 1.5T - 40 1.5T - 60 ASTB WAIT hold time tHSTWTH VDD = +5.0 V 10 % (0.5 + n) T + 5 (0.5 + n) T + 10 ASTB WAIT delay time tDSTWTH VDD = +5.0 V 10 % (1.5 + n) T - 40 (1.5 + n) T - 60 RD WAIT input time tDRWTL VDD = +5.0 V 10 % T - 50 T - 70 RD WAIT hold time tHRWT VDD = +5.0 V 10 % nT + 5 nT + 10 RD WAIT delay time tDRWTH VDD = +5.0 V 10 % (1 + n) T - 40 (1 + n) T - 60 WAIT data input time tDWTID VDD = +5.0 V 10 % 0.5T - 5 0.5T - 10 WAIT WR delay time WAIT RD delay time WR WAIT input time tDWTW tDWTR tDWWTL VDD = +5.0 V 10 % 0.5T 0.5T T - 50 T - 75 WR WAIT hold time tHWWT VDD = +5.0 V 10 % nT + 5 nT + 10 WR WAIT delay time tDWWTH VDD = +5.0 V 10 % (1 + n) T - 40 (1 + n) T - 70 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remark T : TCYK (system clock cycle time) a : 1 in address wait, 0 in the other conditions n : the number of wait (n 0) (4) Refresh timing
Parameter Random read/write cycle time REFRQ low-level pulse width Symbol tRC tWRFQL VDD = +5.0 V 10 % Test Conditions MIN. 3T 1.5T - 25 1.5T - 30 ASTB REFRQ delay time RD REFRQ delay time WR REFRQ delay time REFRQ ASTB delay time REFRQ high-level pulse width tDSTRFQ tDRRFQ tDWRFQ tDRFQST tWRFQH VDD = +5.0 V 10 % 0.5T - 9 1.5T - 9 1.5T - 9 0.5T - 15 1.5T - 25 1.5T - 30 MAX. Unit ns ns ns ns ns ns ns ns ns
Remark T: TCYK (system clock cycle time) 65
PD784031Y
Serial Operation (TA = -40 to +85C, VDD = +2.7 to 5.5 V, AVSS = VSS = 0 V)
(1) CSI
Parameter Serial clock cycle time (SCK0) Symbol tCYSK0 Input Test Conditions External clock when SCK0, SO0 are CMOS input/output MIN. 10/fXX + 380 MAX. Unit ns
Output Serial clock low-level width (SCK0) tWSKL0 Input External clock when SCK0, SO0 are CMOS input/output
T 5/fXX + 150
s
ns
Output Serial clock high-level width (SCK0) tWSKH0 Input External clock when SCK0, SO0 are CMOS input/output
0.5T - 40 5/fXX + 150
s
ns
Output SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time (from SCK0) tSSSK0 tHSSK0 tDSBSK1 CMOS push-pull output (3-wire serial I/O mode) Open drain output (2-wire serial I/O mode), RL = 1 k
0.5T - 40 40 5/fXX + 40 0 5/fXX + 150
s
ns ns ns
tDSBSK2
0
5/fXX + 400
ns
Remarks 1. The values shown in the table above are those in the condition of CL = 100 pF. 2. T : serial clock cycle set by the software. The minimum value is 16/fXX. 3. fXX : oscillation frequency (2) I2C
Parameter Symbol Standard Mode I2C Bus fXX = 4 to 32 MHz MIN. SCL clock frequency Low status hold time of SCL clock High status hold time of SCL clock Data hold time Data setup time SDA, SCL signal rise time SDA, SCL signal fall time Load capacitance of each bus line fSCL tLOW 0 4.7 MAX. 100 High-speed Mode I2C Bus fXX = 8 to 32 MHz MIN. 0 1.3 MAX. 400 kHz Unit
s s
900 ns ns 300 300 400 ns ns pF
tHIGH
4.0
0.6
tHD ; DAT tSU ; DAT tR tF Cb
300 250 1000 300 400
300 100 20 + 0.1Cb 20 + 0.1Cb
66
PD784031Y
(3) IOE1, IOE2
Parameter Serial clock cycle time (SCK1, SCK2) Output Serial clock low-level width (SCK1, SCK2) Output Serial clock high-level width (SCK1, SCK2) Output SI1, SI2 setup time (to SCK1, SCK2) SI1, SI2 hold time (from SCK1, SCK2) SO1, SO2 output delay time (from SCK1, SCK2) SO1, SO2 output hold time (from SCK1, SCK2) tHSOSK When transferring data 0.5tCYSK1 - 40 ns tSSSK1 Internal 16 frequency division tWSKH1 Input Internal 16 frequency division VDD = +5.0 V 10 % tWSKL1 Input Internal 16 frequency division VDD = +5.0 V 10 % Symbol tCYSK1 Input Test Conditions VDD = +5.0 V 10 % MIN. 250 500 T 85 210 0.5T - 40 85 210 0.5T - 40 40 MAX. Unit ns ns ns ns ns ns ns ns ns ns
tHSSK1
40
ns
tDSOSK
0
50
ns
Remarks 1. The values shown in the table above are those in the condition of CL = 100 pF. 2. T: serial clock cycle set by the software. The minimum value is 16/fXX. (4) UART, UART2
Parameter ASCK clock input cycle time Symbol tCYASK Test Conditions VDD = +5.0 V 10 % MIN. 125 250 ASCK clock low-level width tWASKL VDD = +5.0 V 10 % 52.5 85 ASCK clock high-level width tWASKH VDD = +5.0 V 10 % 52.5 85 MAX. Unit ns ns ns ns ns ns
67
PD784031Y
Other Operations
Parameter NMI low-level width NMI high-level width INTP0 low-level width INTP0 high-level width INTP1 to INTP3, CI low-level width INTP1 to INTP3, CI high-level width INTP4, INTP5 low-level width INTP4, INTP5 high-level width RESET low-level width RESET high-level width Symbol tWNIL tWNIH tWIT0L tWIT0H tWIT1L tWIT1H tWIT2L tWIT2H tWRSL tWRSH Test Conditions MIN. 10 10 3tCYSMP + 10 3tCYSMP + 10 3tCYCPU + 10 3tCYCPU + 10 10 10 10 10 MAX. Unit
s s
ns ns ns ns
s s s s
Remark tCYSMP : sampling clock set by the software tCYCPU : CPU operation clock set by the software
A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = AVREF1 = +2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Total errorNote errorNote Symbol Test Conditions MIN. 8 1.0 0.8 1/2 tCONV FR = 1 FR = 0 Sampling time tSAMP FR = 1 FR = 0 Analog input voltage Analog input impedance AVREF1 current AVDD supply current VIAN RAN AIREF1 AIDD1 AIDD2 fXX = 32 MHz, CS = 1 STOP mode, CS = 0 120 180 24 36 -0.3 1000 0.5 2.0 1.0 1.5 5.0 20 AVREF1 + 0.3 TYP. MAX. Unit bit % % LSB tCYK tCYK tCYK tCYK V M mA mA
Linearity
Quantization error Conversion time
A
Note Quantization error is not included. This is expressed in proportion to the full-scale value. Remark tCYK: system clock cycle time
68
PD784031Y
D/A Converter Characteristics (TA = -40 to +85C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Total error Load condition 4 M, 30 pF VDD = AVDD = AVREF2 = +2.7 to 5.5 V AVREF3 = 0 V VDD = AVDD = +2.7 to 5.5 V AVREF2 = 0.75VDD AVREF3 = 0.25VDD Load condition 2 M, 30 pF VDD = AVDD = AVREF2 = +2.7 to 5.5 V AVREF3 = 0 V VDD = AVDD = +2.7 to 5.5 V AVREF2 = 0.75VDD AVREF3 = 0.25VDD Settling time Output resistance Analog reference voltage RO AVREF2 AVREF3 AVREF2, AVREF3 resistance value Reference supply input current RAIREF AIREF2 AIREF3 DACS0, 1 = 55 H Load condition 2 M, 30 pF DACS0, 1 = 55 H 0.75VDD 0 4 0 -5 8 5 0 10 VDD 0.25VDD Symbol Test Conditions MIN. 8 0.6 TYP. MAX. Unit bit %
0.8
%
0.8
%
1.0
%
10
s
k V V k mA mA
69
PD784031Y
Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR Test Conditions STOP mode VDDDR = +2.7 to 5.5 V VDDDR = +2.5 V VDD rise time VDD fall time VDD hold time (from setting STOP mode) STOP release signal input time Oscillation stabilization wait time tRVD tFVD tHVD 200 200 0 MIN. 2.5 10 2 TYP. MAX. 5.5 50 10 Unit V
A A s s
ms
tDREL tWAIT Crystal resonator Ceramic resonator
0 30 5 0 0.9VDDDR 0.1VDDDR VDDDR
ms ms ms V V
Input voltage low-level Input voltage high-level
VIL VIH
Specified
pinsNote
Note RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0/SCL, and P33/SO0/SDA pins
AC Timing Test Point
VDD - 1 V 0.8VDD or 2.2 V Test Points 0.45 V 0.8 V 0.8 V 0.8VDD or 2.2 V
70
PD784031Y
Timing Waveform
(1) Read operation
tWSTH ASTB tSAST tHSTLA A8 to A19 tDSTID tDRST
tDAID AD0 to AD7 tDSTR tDAR RD tWRL tFRA tDRID
tHRA
tHRID tDRA
(2) Write operation
tWSTH ASTB tSAST tHSTLA A8 to A19 tDSTOD tDWST
tHWA AD0 to AD7 tDSTW tDAW WR tWWL tDWOD tSODW tHWOD
71
PD784031Y
Hold Timing
ADTB, A8 to A19, AD0 to AD7, RD, WR tFHQC tDCFHA HLDRQ tDHQHHAH HLDAK tDHQLHAL tDHAC
External WAIT Signal Input Timing
(1) Read operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8 to A19
AD0 to AD7 tDAWT RD tDRWTL WAIT tHRWT tDRWTH tDWTR tDWTID
(2) Write operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8 to A19
AD0 to AD7 tDAWT WR tDWWTL WAIT tHWWT tDWWTH tDWTW
72
PD784031Y
Refresh Timing Waveform
(1) Random read/write cycle
tRC ASTB
WR tRC RD tRC tRC tRC
(2) When refresh memory access is simultaneous with read, write
ASTB
RD, WR tDSTRFQ tDRFQST tWRFQH
REFRQ tWRFQL
(3) Refresh after read
ASTB tDRFQST RD tDRRFQ REFRQ tWRFQL
(4) Refresh after write
ASTB tDRFQST WR tDWRFQ REFRQ tWRFQL
73
PD784031Y
Serial Operation
(1) CSI
tWSKL0 SCK tCYSK0 SI tDSBSK1 SO tHSBSK1 tSSSK0 tHSSK0 Input Data tWSKH0
Output Data
(2) I2C
tR tF tHIGH tLOW
SCL
SDA
tHD ; DAT
tSU ; DAT
(3) IOE1, IOE2
tWSKL1 SCK tCYSK1 SI tDSOSK SO tHSOSK tSSSK1 tHSSK1 tWSKH1
Input Data
Output Data
(4) UART, UART2
tWASKH tWASKL
ASCK, ASCK2 tCYASK
74
PD784031Y
Interrupt Input Timing
tWNIH tWNIL
NMI
tWIT0H
tWIT0L
INTP0
tWIT1H
tWIT1L
CI, INTP1 to INTP3
tWIT2H
tWIT2L
INTP4, INTP5
Reset Input Timing
tWRSH tWRSL
RESET
75
PD784031Y
External Clock Timing
tWXH tWXL
X1 tXR tCYX tXF
Data Retention Characteristics
STOP Mode Setting
VDD tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
NMI (release by falling edge)
NMI (release by rising edge)
76
PD784031Y
14. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end
CD
S Q R
80 1
21 20
F G H P I
M
J K M N L
NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 17.20.4 14.00.2 14.00.2 17.20.4 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.7 0.10.1 55 3.0 MAX.
INCHES 0.6770.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.0040.004 55 0.119 MAX. S80GC-65-3B9-4
Remark Dimensions and materials of ES products are the same as those of mass-produced products.
77
PD784031Y
80 PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end
C
D
S R Q
80 1
21 20
F G P H I
M
J K M
N
NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 3 +7 -3 1.70 MAX. INCHES 0.6770.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.008 0.032 0.032 0.013 +0.002 -0.003 0.005 0.026 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.007 +0.001 -0.003 0.004 0.0550.004 0.0050.003 3 +7 -3 0.067 MAX. P80GC-65-8BT
Remark Dimensions and materials of ES products are the same as those of mass-produced products.
78
PD784031Y
80-PIN PLASTIC TQFP (FINE PITCH) (12 x 12 mm)
A B
60 61
41 40
detail of lead end
C
D
S Q
80
21 1 20
F
G
H
I
M
J
K
P
N L
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145 +0.055 -0.045 0.10 1.05 0.050.05 55 1.27 MAX. INCHES 0.551 +0.009 -0.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.551 +0.009 -0.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.041 0.0020.002 55 0.050 MAX. P80GK-50-BE9-4
Remark Dimensions and materials of ES products are the same as those of mass-produced products.
M
R
79
PD784031Y
15. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions (1/2) (1) PD784031YGC-3B9: 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Duration: 30 sec. max. (at 210C or above), Number of times: 3 times max. VPS Package peak temperature: 215C, Duration: 40 sec. max. (at 200C or above), Number of times: 3 times max. Solder bath temperature: 260C max., Duration: 10 sec. max., Number of times: Once, Preliminary heat temperature: 120C max. (Package surface temperature) Pin temperature: 300C max. Duration: 3 sec. max. (per device side) VP15-00-3 Symbol IR35-00-3
Wave soldering
WS60-00-1
Partial heating
--
Caution
Use of more than one soldering method should be avoided (except in the case of partial heating).
(2) PD784031YGC-8BT: 80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Duration: 30 sec. max. (at 210C or above), Number of times: Twice max. Package peak temperature: 215C, Duration: 40 sec. max. (at 200C or above), Number of times: Twice max. Solder bath temperature: 260C max., Duration: 10 sec. max., Number of times: Once, Preliminary heat temperature: 120C max. (Package surface temperature) Pin temperature: 300C max. Duration: 3 sec. max. (per device side) Symbol IR35-00-2
VPS
VP15-00-2
Wave soldering
WS60-00-1
Partial heating
--
Caution
Use of more than one soldering method should be avoided (except in the case of partial heating).
80
PD784031Y
Table 15-1. Surface Mounting Type Soldering Conditions (2/2) (3) PD784031YGK-BE9: 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Duration: 30 sec. max. (at 210C or above), Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking required at 125C) Do not bake devices by packing them in non-heat resistant trays or packing materials such as magazine cases and tapes. Use heat-resistant trays. Package peak temperature: 215C, Duration: 40 sec. (at 200C or above), Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking required at 125C) Do not bake devices by packing them in non-heat resistant trays or packing materials such as magazine cases and tapes. Use heat-resistant trays. Partial heating Pin temperature: 300C max. Duration: 3 sec. max. (per device side) -- Symbol IR35-107-2
VPS
VP15-107-2
Note For the storage period after dry-pack decapsulation, storage conditions are max. 25C, 65 % RH. Caution Use of more than one soldering method should be avoided (except in the case of partial heating).
81
PD784031Y
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for supporting development of a system using the PD784031Y. Language Processor Software RA78K4Note 1 CC78K4Note 1 CC78K4-LNote 1 Assembler package common to 78K/IV Series C compiler package common to 78K/IV Series C compiler library source file common to 78K/IV Series
PROM Writing Tool PG-1500 PA-78P4026GC PA-78P4038GK PA-78P4026KK PG-1500 controllerNote 2 Debugging Tool IE-784000-R IE-784000-R-BK IE-784038-R-EM1 IE-784000-R-EM IE-70000-98-IF-B IE-70000-98N-IF IE-70000-PC-IF-B IE-78000-R-SV3 EP-78230GC-R EP-78054GK-R EV-9200GC-80 TGK-080SDW EV-9900 SM78K4Note 3 ID78K4Note 3 DF784038Note 4 Real-time OS RX78K/IVNote 4 MX78K4Note 2 Real-time OS for 78K/IV Series OS for 78K/IV Series Interface adapter when PC-9800 Series (except notebook type) is used as host machine Interface adapter and cable when notebook type PC-9800 Series is used as host machine Interface adapter when IBM PC/ATTM is used as host machine Interface adapter and cable when EWS is used as host machine Emulation probe for 80-pin plastic QFP (GC-3B9 and GC-8BT types) common to In-circuit emulator common to 78K/IV Subseries Break board common to 78K/IV Series Emulation board for evaluation of PD784038Y Subseries PG-1500 control program PROM programmer Programmer adapter connected to PG-1500
PD784038Y Subseries
Emulation probe for 80-pin plastic TQFP (fine pitch) (GK-BE9 type) common to
PD784038Y Subseries
Socket mounted on board of target system created for 80-pin plastic QFP (GC-3B9 and GC-8BT types) Adapter mounted on board of target system created for 80-pin plastic TQFP (fine pitch) (GK-BE9 type) Jig used to remove PD78P4038YKK-T from EV-9200GC-80 System simulator common to 78K/IV Series Integrated debugger for IE-784000-R Device file for PD784038Y Subseries
82
PD784031Y
Notes 1. * PC-9800 Series (MS-DOSTM) based * IBM PC/AT and compatible machine (PC DOSTM, WindowsTM, MS-DOS, IBM DOSTM) based * HP9000 Series 700TM (HP-UXTM) based * SPARCstationTM (SunOSTM) based * NEWSTM (NEWS-OSTM) based 2. * PC-9800 Series (MS-DOS) based * IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) based 3. * PC-9800 Series (MS-DOS + Windows) based * IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) based * HP9000 Series 700 (HP-UX) based * SPARCstation (SunOS) based 4. * PC-9800 Series (MS-DOS) based * IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) based * HP9000 Series 700 (HP-UX) based * SPARCstation (SunOS) based Remarks 1. RA78K4, CC78K4, SM78K4, and ID78K4 are used in combination with DF784038. 2. TGK-080SDW is manufactured by TOKYO ELETECH Corporation. representative when purchasing it. Consult your local NEC sales
83
PD784031Y
APPENDIX B. RELATED DOCUMENTS
Documents Related to Device
Document Name English Document No. Japanese U11504J U10741J U10742J U11316J U11091J U10905J U10594J U10595J U10095J
PD784031Y Data Sheet PD784035Y, 784036Y, 784037Y, 784038Y Data Sheet PD78P4038Y Data Sheet PD784038, 784038Y Subseries User's Manual - Hardware PD784038Y Subseries Special Function Register Table
78K/IV Series User's Manual - Instruction 78K/IV Series Instruction Table 78K/IV Series Instruction Set 78K/IV Series Application Note - Software Basics
This manual U10741E U10742E U11316E - U10905E - - -
Documents Related to Development Tools (User's Manuals)
Document Name English RA78K4 Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K4 Series Operation Language CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller - PC-9800 Series (MS-DOS) Based PG-1500 Controller - IBM PC Series (PC DOS) Based IE-784000-R IE-784038-R-EM1 EP-78230 EP-78054GK-R SM78K4 System Simulator - Windows Based SM78K Series External Part User Open Interface Specifications ID78K4 Integrated Debugger - Windows Based ID78K4 Integrated Debugger - HP9000 Series 700 (HP-UX) Based Reference Reference Reference U11334E - EEU-1402 - - - EEU-1335 EEU-1291 U10540E EEU-1534 U11383E EEU-1515 EEU-1468 U10093E U10092E U10440E To be released soon Document No. Japanese U11334J U11162J EEU-817 EEU-960 EEU-961 U12322J U11940J EEU-704 EEU-5008 EEU-5004 U11383J EEU-985 EEU-932 U10093J U10092J U10440J U11960J
Caution
The above related documents are subject to change without prior notice. Be sure to use the latest version when starting design.
84
PD784031Y
Documents Related to Embedded Software (User's Manual)
Document Name English 78K/IV Series Real-time OS Basics Installation Debugger 78K/IV Series OS MX78K4 Basics U10603E U10604E - - Document No. Japanese U10603J U10604J U10364J U11779J
Other Documents
Document Name English IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices Reliability Quality Control on NEC Semiconductor Device Electric Static Discharge (ESD) Test Semiconductor Devices Quality Assurance Guide Microcomputer Product Series Guide C10535E C11531E C10983E - MEI-1202 - C10943X C10535J C11531J C10983J MEM-539 C11893J U11416J Document No. Japanese
Caution
The above related documents are subject to change without prior notice. Be sure to use the latest version when starting design.
85
PD784031Y
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee outpin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
86
PD784031Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
87
PD784031Y
Caution
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
EEPROM and IEBus are trademarks of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5

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